Thursday, 6 October 2016

Adapteva tapes out Epiphany-V: A 1024-core 64-bit RISC processor

Firstly, what is it?

Adapteva's new silicon plan is a pretty cute 1024-core chip in 16nm FinFet technology, joining Pezy & Kilocore in the 1k core stakes. Each in-order dual-issue RISC processor has some SRAM and the ISA is not all that different to RISC-V conceptually but it is different. This generation has added 64-bit addressing, ints & FP, and custom extensions for deep learning, comms, and crypto.

This project is a follow on from the successful kickstarter than brought the 16-core Epiphany into the public consciousness with a Xilinx Zynq and Epiphany small factor board that attracted nearly 5,000 backers.

The new chip supports 128 point-to-point I/O links for chip to chip comms with addressing that scales to support a billion cores and 1 Petabyte of total memory. Those I/O links remind me a lot of a transputer, which I think is a good thing. Yeah, I'm old enough to have written Occam for a transputer.

Many multi-core chips, such as the original Tilera, raised concerns due to a tendency of much code to starve their cores of memory with limited external memory support. Epiphany addresses this by not having any memory controllers at all for external memory. You must use an external controller, such as an FPGA, if you want to attached external RAM. This is an interesting solution that will suit some problems and not others. SRAM is 53.3% of the total die area in this case. Not an unreasonable balance perhaps.

Tapeout is not production, the chip is in the production queue. Power dissipation and frequency expectations are not being shared by the Adapteva yet. Perhaps expect >= 500MHz and at least 75GFLOPS/Watt which means equal to or better than 1TFLOPS and better than 13.3W per TFLOPS. Fingers crossed it has better success than the awesome but late and buggy T9000 transputer that resulted in the decline of Inmos.

Epiphany-V has a physically imposing chip specification:

Must have been a large team I hear you say? Nope: try one and a bit people.

Adapteva's Andreas Olofsson has meandered over from being an impressive EE to an outright EE God.

Around 80% of the 1024 core work from Adapteva was from Andreas as we can see in this table:

The truly impressive aspect is that instead of requiring a large team of hundreds of people, a small team, or mainly just one person, Andreas, has managed to build a 4.5B gate chip design with modern design rules. This is very impressive, even if there have been many replications of various instances with none of the nine hard macro blocks replicated being larger than around 50k gates.

This chipe has long been a goal for Andreas with a paper published in 2011, "A 1024-core 70 GFLOP/W Floating Point Manycore Microprocessor", describing the early view. Funding was not there but it looks like some DARPA funding has helped reify the dream and quite quickly. Here is the new paper on the implementation of the Epiphany-V, "Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip."

You program the beast with GCC-5 and GDB-7.10. It's binary compatible to the older versions so you can expect all these programming frameworks to work somewhat and be further improved:

Sixteen of these chips on a board for 200~300W processing card would be a nice product that may give a Nvidia P100 or Intel Knight's Landing a run for their money, iff you can live within the memory constraints. Also, if the chip size is quadrupled it is still smaller in area than KNL and P100, and similar to Broadwell. 4,096 cores, or more of something (RAM), should be easy enough if someone will pay for it.

The power of one indeed. This exemplar is not just impressive but inspiring for people like me who are working all alone in a bubble hoping to build something a bit new and different.

Congratulations to Andreas and the rest of the Adapteva team with all fingers crossed for the sampling, yield, clock rates, and power consumption yet to finalise. Well done.


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